Excavating
Patent
1985-05-06
1986-07-01
Atkinson, Charles E.
Excavating
371 40, G06F 1110
Patent
active
045984034
DESCRIPTION:
BRIEF SUMMARY
DESCRIPTION
1. Technical Field
This invention relates to an encoding method for error correction which employs a feedback type cross-interleave.
2. Background Art
In the prior art, it is known that an audio signal sequence, for example, can be sampled at every sample (word) of a predetermined number, an error correction redundant code can be added thereto, an interleave operation can be performed to delay PCM data of the predetermined numbered sample (word) and error correction code with respectively different delay amounts and an error detection code can be added thereto, and the so modified audio signal sequence recorded and reproduced. As one of such interleaves, there has been proposed a cross-interleave technique in which a first redundant code is added to PCM words of the predetermined number which are in a first arrangement state, a second redundant code is added to the PCM words of the predetermined number which are put into a second arrangement state after the interleave operation, and a third redundant code is added to the PCM words of the predetermined number which are put into a third arrangement state after the interleave operation and after the first and second redundant codes have been added. In the cross-interleave technique, since each word of the PCM data is included in two sequences which respectively generate the first redundant code and the second redundant code, it can improve error correction ability as compared with ordinary interleave. In accordance with a feedback-type cross-interleave, the second redundant code is fed back to the first arrangement state so as to include the second redundant code in the sequence which generates the first redundant code so that the error correction ability thereof can be improved much more.
FIG. 1 shows an arrangement of a block completion type encoder 1 for a non-feedback type cross-interleave, where PCM data such as audio PCM data and the like are divided into one interleave block (of n words.times.m blocks). In the representation of W(m, n), m denotes a block number included within an interleave block, while n denotes a word number included within the interleave block. From data of respective blocks within the interleave block is formed a first parity data Pm by a modulus-2 (mod. 2) adder 2. ##EQU1##
Next, a memory circuit 3 carries out interleave processing. The memory circuit 3 has a capacity large enough to memorize the data of one interleave block and operates to delay respective words of W(m, 0), W(m, 1) . . . W(m, n-1), Pm by d blocks each. PCM data and parity data which were put into the second arrangement state by this delay processing are supplied to a modulus-2 (mod. 2) adder 4 which forms a second parity data Qm. ##EQU2## where the block numbers m-kd and m-nd are calculated by (mod. m) and completed at each one interleave block.
FIG. 2 illustrates such block completion type-cross-interleave where a line in the vertical direction in the figure represents a data sequence which generates the first parity Pm, while a line in the obilique direction represents a data sequence which generates the second parity Qm. As shown in the states of broken lines in FIG. 2, the block numbers of the data which generate the second parity Qm are calculated by (mod. m) so that the block numbers may sometimes be returned to smaller numbers. For this reason, the memory circuit with the capacity of one interleave block amount must be required. All PCM words within one interleave block are contained in two parity generation sequences, and these two parity generation sequences are made different at every words within one interleave block.
There is further provided a memory circuit 5 which delays n PCM data sequences and two parity data sequences by 0, (D-d), 2(D-d) . . . , n(D-d), (n+1)(D-d) blocks. In the case of this delay, the block number is calculated by (mod. m), too. Data of (n+2) words extracted from the respective data sequences which were delayed by the memory circuit 5 are supplied to a CRC generator 6 which forms a CRC code. The CRC code is used fo
REFERENCES:
patent: 4312070 (1982-01-01), Coombes et al.
patent: 4336612 (1982-06-01), Inoue et al.
patent: 4398292 (1983-08-01), Doi et al.
patent: 4413340 (1983-11-01), Odaka et al.
Atkinson Charles E.
Eslinger Lewis H.
Sinderbrand Alvin
Sony Corporation
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