System for treatment of single bit error in buffer storage unit

Details System for treatment of single bit error in buffer storage unit System for treatment of single bit error in buffer storage unit

1983-11-07

1986-07-01

Harkcom, Gary V.

Excavating

371 13, G06F 1110

Patent

active

045984026

ABSTRACT:
In a data processing device comprising a main storage unit, a buffer storage unit, and an error check and correction circuit, when data held in the buffer storage unit contains a single-bit error, the data containing the single-bit error is moved out from the buffer storage unit by generating a predetermined number of addresses having the same number (memory sector) as the data containing the single-bit error. The data is then corrected by the error check and correction circuit, and the corrected data is stored in the main storage unit.

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Kerchmar et al., "Use of Memory Cache for Main Memory Failure Mode Analysis", IBM Technical Disclosure Bulletin, vol. 25, No. 4, Sep. 1982, pp. 1849-1852.

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