Multiprocessor system having offset address setting

Details Multiprocessor system having offset address setting Multiprocessor system having offset address setting

1993-12-07

1995-10-03

Teska, Kevin J.

Boots, shoes, and leggings

395375, 39542107, 395476, 395419, 3642448, 364228, 36424531, 3642551, 3642581, 364259, 364DIG1, G06F 926, G06F 1200

Patent

active

054559200

ABSTRACT:
A multiprocessor system includes the first microcomputer (1) having the first memory (4); the second microcomputer (9) having the second memory (12), the dual port third memory (14), and an offset register (22); buses (18-20) for connecting the first and second microcomputers; an address setting unit (21) provided in the second microcomputer for composing an address value supplied by the first microcomputer and a value set in the offset register to feed address data to the third memory.

REFERENCES:
patent: 4121283 (1978-10-01), Walker
patent: 4796232 (1989-01-01), House
patent: 4999768 (1991-03-01), Hirokawa
patent: 5327541 (1994-07-01), Reinecke et al.
"Serial Multiprocessing Architecture for Signal Processing," IBM Technical Disclosure Bulletin, vol. 32, No. 3B, Aug. 1989, IBM Corp.
Livingston, et al., "Transparent Hardware Address Offset for Use in a Common Memory, Multi-Processor Environment," IBM Technical Disclosure Bulletin, vol. 26, No. 11, Apr. 1984, IBM Corp.

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