Error detection and recovery in parallel/serial buses

Details Error detection and recovery in parallel/serial buses Error detection and recovery in parallel/serial buses

Filed on

1993-06-01

Date issued

1995-10-03

Examiner

Cosimano, Edward R.

Patent Class

Excavating

Other Related Categories

364550, 370103, 3701051, G06F 1520, H04J 306

Type

Patent

Status

active

Patent number

054558301

Description

ABSTRACT:
A system and method for asynchronously transmitting data blocks, in parallel, across multiple fibers in a serial manner. Frame groups are provided as a mechanism to transmit associated data serially on each fiber and tie the data being transmitted together. The frame groups do not have sequence numbers, therefore, the receiver determines which frames are part of a frame group by the arrival times of the individual frames. In one embodiment, the transceivers for each member of the parallel bus asynchronously achieve synchronism at each end of the fiber. Thus the need for a common clock is eliminated. The receivers on each side of the bus determine the relative skew for each conductor by performing skew measurements on a calibration message generated by the transmitters on the other side of the bus. When the skew on all conductors, viewed from both sides of the bus, has been determined, the skew values are exchanged across the bus, thus enabling the transmitters to set proper frame spacing.

REFERENCES:
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patent: 4729123 (1988-03-01), Wheen
patent: 4827477 (1989-05-01), Avaneas
patent: 4959833 (1990-09-01), Mercola et al.
patent: 4970714 (1990-11-01), Chen et al.
patent: 5222079 (1993-06-01), Rasor
patent: 5267240 (1993-11-01), Bartow et al.
patent: 5313501 (1994-05-01), Thacker

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