Decimation filter and method

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36472613, G06F 1531

Patent

active

054557828

ABSTRACT:
Programmable decimation filter made of integrators and combs with a shortened first integrator register and with a single subtractor plus memory for the combs subtractions. The comb subtractions are serially performed with read/write accesses to the memory. A shifter between the first and second integrator registers provides application to low decimation rates and the shortened register relates to device error rate at high decimation rates.

REFERENCES:
patent: 4270026 (1981-05-01), Shenoi et al.
patent: 4872129 (1989-10-01), Pfeifer et al.
patent: 4999798 (1981-03-01), McCaslin et al.
patent: 5079734 (1992-01-01), Riley

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