Protocol method for validating an input protocol specification

Details Protocol method for validating an input protocol specification Protocol method for validating an input protocol specification

1995-05-12

1997-08-05

Beausoliel, Jr., Robert W.

G06F 1100

Patent

active

056550758

ABSTRACT:
Validation of an input protocol is divided into two steps. In the first processing step, a state. transition graph of each process including only executable state transitions of each process is generated according to transition information which the protocol specification has, and at the same time, protocol errors related to behavior of the process is detected. In the second processing step, reachable system states among system states defined by combinations of individual process states and individual channel states are successively generated according to transition information which the state transition graph of each process has, and a system state of the generated reachable system states which cannot transit further is detected as a deadlock. In the protocol validation method, every system state can be erased from the memory when a deadlock detection for it is completed, and searching the generated system states is not necessary, and some additional techniques for more efficient validation can be applied. Therefore the protocol validation method enables validation with a practical period of time even for a large-scale or complicated protocol specification without requiring a large-capacity memory.

REFERENCES:
patent: 4694422 (1987-09-01), Kakuda et al.
patent: 4754400 (1988-06-01), Wakahara et al.
patent: 5515504 (1996-05-01), Le Van Suu
C. H. West: "General Technique for Communications Protocol Validation", IBM J. Res. Devel., Jul. 1978.
D. Brand and P. Zafiropulo: "Research Report on Communicating Finite-state Machines", IBM Res. Rep. RZ 1053, 1981.

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