Making guard ring for reducing pattern sensitivity in MOS/LSI dy

Details Making guard ring for reducing pattern sensitivity in MOS/LSI dy Making guard ring for reducing pattern sensitivity in MOS/LSI dy

1985-02-15

1986-07-01

Roy, Upendra

Metal treatment

Compositions

Heat treating

29571, 29576B, 29577C, 148187, 148DIG82, 357 91, H01L 2126, H01L 2704

Patent

active

045978050

ABSTRACT:
An MOS/LSI type dynamic RAM with single 5 V supply and grounded substrate employs a guard ring surrounding the cell array to prevent pattern sensitivity in testing. The guard ring is an N+ region biased at Vdd over a deep P+ region in a P-substrate, producing a built-in electric field which attracts diffusing minority carriers into a collecting junction. A standard process for making double-level poly memory devices is modified by adding a P+ implant and deep drive-in prior to field oxidation.

REFERENCES:
patent: 4125933 (1978-11-01), Baldwin et al.
patent: 4164751 (1979-08-01), Tasch, Jr.
patent: 4206471 (1980-06-01), Hoffmann et al.
patent: 4290471 (1980-06-01), Klein et al.
patent: 4313253 (1982-02-01), Henderson, Sr.
patent: 4333225 (1982-06-01), Yeh

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