Method and apparatus for indicating overflow status of bit-varia

Details Method and apparatus for indicating overflow status of bit-varia Method and apparatus for indicating overflow status of bit-varia

1995-08-04

2000-01-04

Mai, Tan V.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

G06F 738

Patent

active

060120770

ABSTRACT:
An apparatus and a method for indicating the computational adder overflow status of bit-variable data employing a pipelining adder. An adder is provided with a first input port and a second input port, for adding a multiple-bit data input from the second input port. A plurality of shift registers receive and store in parallel a plurality of multiple-bit data output from the adder, and sequentially output the plurality of multiple-bit data to the second input port of the adder in response to a clock signal. A comparing circuit simultaneously receives and compares a multiple-bit data output from the adder and a multiple-bit data output from a plurality of shift registers. An overflow arbitrating unit arbitrates the overflow status of each multiple-bit data in accordance with a comparing result from the comparing circuit as well as a selective signal.

REFERENCES:
patent: 5369438 (1994-11-01), Kim
patent: 5745397 (1998-04-01), Nadehara

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