Method and apparatus for coupling multiple independent on-chip V

Details Method and apparatus for coupling multiple independent on-chip V Method and apparatus for coupling multiple independent on-chip V

1996-10-18

1997-08-05

Deboer, Todd

Electricity: electrical systems and devices

Safety and protection of systems and devices

Transient responsive

361 91, 361 56, H02H 904

Patent

active

056548621

ABSTRACT:
A single clamp circuit for integrated circuits with multiple V.sub.dd power pins by coupling the various V.sub.dd busses to an ESD clamped V.sub.dd bus or pseudo- V.sub.dd bus via diodes. The diodes will provide coupling from any V.sub.dd bus to the clamp circuit during a positive ESD transient. A diode for each V.sub.dd bus and a single clamp circuit can be much more area efficient than a single clamp circuit for each V.sub.dd bus. During normal operation, the diodes will become weakly forward biased due to the leakage current of the clamp circuit. Small signal noise will tend not to be coupled from one bus to the other because of the high impedance of the diodes. For a large positive noise transient on one bus, the other bus diode will reverse bias, thus decoupling the signal from the other busses. A large negative noise transient on one bus will cause its diode to reverse bias thus decoupling it from the other busses. To help filter small signal noise and provide an additional charged device model discharge path, a capacitor is added from the pseudo or ESD V.sub.dd to substrate ground. Also disclosed is an ESD protection scheme for allowing a pad voltage to exceed the power supply voltage without using an avalanching junction as the ESD protection means. Further disclosed is a clamp scheme for allowing the transistors of the power supply clamp to see voltages lower than that of the pad voltage which exceed the process reliability limits.

REFERENCES:
patent: 4698720 (1987-10-01), Finaurini
patent: 4736271 (1988-04-01), Mack et al.
patent: 5034845 (1991-07-01), Murakami

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