Method for fabricating a FET having a dielectrically isolated ga

Details Method for fabricating a FET having a dielectrically isolated ga Method for fabricating a FET having a dielectrically isolated ga

1994-01-03

1995-10-03

Fourson, George

Fishing, trapping, and vermin destroying

437 41, 437184, 437192, 437944, H01L 21265

Patent

active

054551838

ABSTRACT:
A HIGFET having a gate with a pad which is isolated from the FET heterostructure wafer by a dielectric layer to minimize leakage current between the gate and the wafer. The method of production of this device involves application of the gate metal only over the active area of the FET and a photo resist covering on the gate metal. The wafer, including the area covered by the photo resist, is covered with the dielectric layer. The photo resist layer is removed along with the dielectric layer from over the gate metal. Another layer of gate metal is formed on the preexisting gate metal including a gate pad on part of the remaining dielectric layer.

REFERENCES:
patent: 4529919 (1985-07-01), Fabian
patent: 4599791 (1986-07-01), Focht et al.
patent: 4605470 (1986-08-01), Gwozdz et al.
patent: 5160492 (1992-11-01), Wang et al.
patent: 5210042 (1993-05-01), Oshikowa
patent: 5328854 (1994-07-01), Vakhshoori et al.
IBM Technical Disclosure Bulletin, vol. 33, No. 7, pp. 3934, Dec. 1990.

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