Flexible distributed bus priority network

Details Flexible distributed bus priority network Flexible distributed bus priority network

1990-10-05

1992-09-22

Heckler, Thomas M.

Boots, shoes, and leggings

364DIG1, 3642292, 3642427, 3642413, 3642705, G06F 1337

Patent

active

051504669

ABSTRACT:
A multiprocessor system includes a system management facility (SMF) unit, a plurality of central subsystem (CSS) units, a plurality of memory subsystem units and first and second pluralities of input/output units which connect in common to a system bus. Requests are transferred between a pair of units on a distributed bus priority network included as part of the system bus on the basis of the unit's physical position on the bus relative to one end of the bus. The SMF unit positioned at the high priority end of the bus includes fast recovery bus request logic circuits which connect to the high priority request line of the priority network. Each of the CSS units positioned after the SMF unit on either side of the memory subsystems includes bus request logic circuits which connect only to the low priority request line. The memory subsystems each include bus request logic circuits which connect to both the high and low priority request lines for accepting and granting cycles from higher and lower priority units. This enables the positioning of the first and second pluralities of input/output units positioned below the memory subsystems to operate as high and low priority requestors.

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patent: 4096569 (1978-06-01), Barlow
patent: 4402040 (1983-08-01), Evett
patent: 4470112 (1984-09-01), Dimmick
patent: 4556939 (1985-12-01), Read
patent: 4559595 (1985-12-01), Boudreau et al.
patent: 4611276 (1986-09-01), Vinot

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