Method and apparatus for generating an end-around carry in a flo

Details Method and apparatus for generating an end-around carry in a flo Method and apparatus for generating an end-around carry in a flo

1998-01-16

2000-05-09

Ngo, Chuong Dinh

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

708501, G06F 738

Patent

active

060617071

ABSTRACT:
An apparatus for generating an end-around carry to an end-around carry adder in a floating-point pipeline within a computer system is disclosed. The apparatus for generating an end-around carry includes a shift-comparison logic circuit, a sign-comparison circuit, and a logic gate. The shift-comparison logic circuit produces a shift-count signal and the sign-comparison logic circuit produces an effective operation signal. Coupled to the shift-comparison logic circuit and the sign-comparison logic circuit, the logic gate combines the shift-count signal and the effective operation signal with a carry-out signal generated by an end-around carry adder to provide an end-around carry signal for the end-around carry adder.

REFERENCES:
patent: 4969118 (1990-11-01), Montoye et al.
patent: 5040138 (1991-08-01), Maher, III
patent: 5241493 (1993-08-01), Chu et al.
patent: 5790445 (1998-08-01), Eisen et al.
patent: 5880983 (1999-03-01), Elliott et al.

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