Semiconductor device trench isolation structure with polysilicon

Details Semiconductor device trench isolation structure with polysilicon Semiconductor device trench isolation structure with polysilicon

1999-01-26

2000-09-19

Powell, William

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

H01L 21302

Patent

active

061211486

ABSTRACT:
A semiconductor device, polysilicon-contacted trench isolation structure that provides improved electrical isolation stability, a method of operating a polysilicon-contacted trench isolated semiconductor device, and a process for manufacturing a polysilicon-contacted trench isolation structure. The trench isolation structure includes an isolation trench formed in a semiconductor substrate. The isolation trench has a layer of trench lining oxide, a layer of trench lining silicon nitride and a trench fill polysilicon (poly 1) layer. Exposed lateral surfaces of the poly 1, which extend above the trench lining silicon nitride, are contacted to another layer of polysilicon (poly 2). The method of operation includes applying a bias voltage to the trench fill poly 1 layer via poly 2. The process for manufacture includes etching an isolation trench that extends through a layer of field oxide and into a semiconductor substrate. After forming layers of trench lining oxide, trench lining silicon nitride and trench fill poly 1 in the isolation trench, the trench lining silicon nitride is etched back to expose lateral surfaces of the trench fill poly 1. A poly 2 layer is then deposited and makes contact with the exposed lateral surfaces of the trench fill poly 1.

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Katsumata, Y., et al: Sub-20 ps ECL Bipolar Technology with High Breakdown Voltage, ESSDERC, pp. 133-136 (1993).
Poon, S. et al.: A Trench Isolation Process for BiCMOS Circuits, IEEE Bipolar circuits and Technology Meeting 3.3, pp. 45-48 (1993).
Rung, R. et al.: Deep Trench Isolated CMOS Devices, IDEM, vol. 82, pp. 237-240, (1982).
Yindeepol, W. et al. Methods of Forming and Planarizing Deep Isolation Trenches in a Silicon-On-Insulator (SOI) Structure, Co-pending U.S. application 08/816,490 filed Mar. 13, 1997.

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