Multiplex communications – Communication techniques for information carried in plural... – Combining or distributing information via time channels
Patent
1997-08-25
2000-05-09
Nguyen, Chau
Multiplex communications
Communication techniques for information carried in plural...
Combining or distributing information via time channels
712 33, H04J 304
Patent
active
06061367&
ABSTRACT:
A processor having a pipelining structure, in particular with a superscalar architecture, includes a configurable logic unit, an instruction memory, a decoder unit, an interface device, a programmable structure buffer, an integer/address instruction buffer and a multiplex-controlled s-paradigm unit linking contents of an integer register file to a functional unit with programmable structures and having a large number of data links connected by multiplexers. The s-paradigm unit has a programmable hardware structure for dynamic reconfiguration/programming while the program is running. The functional unit has a plurality of arithmetic units for arithmetic and/or logic linking of two operands on two input buses to produce a result on an output bus, a plurality of compare units having two input buses and one output bit, a plurality of multiplexers having a plurality of input buses and one or two output buses and being provided between the arithmetic units, the compare units and the register file, and a plurality of demultiplexers having one input bit and a plurality of output bits. A method is also provided for high-speed calculation with pipelining.
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Greenberg Laurence A.
Lerner Herbert L.
Nguyen Chau
Nguyen Kim T.
Siemens Aktiengesellschaft
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