Memory integrated circuit supporting maskable block write operat

Details Memory integrated circuit supporting maskable block write operat Memory integrated circuit supporting maskable block write operat

1998-07-14

2000-05-09

Nelms, David

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365200, 3652257, G11C 800

Patent

active

060612916

ABSTRACT:
A memory circuit column decoder is provided with an array of fuses that can be selectively blown to indicate a fuse address of a defective column of a memory array to be substituted by a redundant column. The memory circuit column decoder also includes a decoder that receives a mask that selectively masks out certain columns of a group of columns from being written during a block write operation, and the fuse address from the array of fuses. The decoder generates a signal for disabling the redundant column during a block write operation when the mask masks out the defective column.

REFERENCES:
patent: 5612918 (1997-03-01), McClure
patent: 5706292 (1998-01-01), Merritt
patent: 5812466 (1998-09-01), Lee et al.

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