Semiconductor integrated circuit device comprising scan paths ha

Details Semiconductor integrated circuit device comprising scan paths ha Semiconductor integrated circuit device comprising scan paths ha

1991-03-22

1992-09-22

Karlsen, Ernest F.

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

With rotor

371 223, G01R 3128

Patent

active

051500442

ABSTRACT:
Three shift path circuits (10', 20', 30') each comprising a bypass circuit are connected in series between a test data input (TDI) and a test data output (TDO). Each shift path circuit constitutes a design definition test data register connected to a circuit to be tested. Design modification of a testing circuit can be minimized by selectively operating the bypass circuit provided in a shift path circuit, even if there is circuit modification in the circuit to be tested. The period of time required for testing circuits to be tested is reduced.

REFERENCES:
patent: 4698588 (1987-10-01), Hwang et al.
patent: 4860290 (1989-08-01), Daniels et al.
JTAG Boundary-Scan Architecture Standard Proposal, Version 2.0, 1988.
IEEE Standard Test Access Port and Boundary-Scan Architecture, 1990.
Standard Test Access Port and Boundary-Scan Architecture (Draft), Test Technology Technical Committee of the IEEE Computer Society, 1989.
The IEEE High Performance Systems publication entitled "1149.1, A Designer's Reference", Evanczuk, 1989, pp. 52-60.
The IEEE High Performance Systems publication entitled "Handling the Transition to Boundary Scan for Boards", Hansen et al., 1989, pp. 74-81.
The IEEE High Performance Systems publication entitled "Bringing 11.49.1 ito the Real World", McClean et al, 1989, pp. 61-70.
The VLSI Systems Design publication entitled "A CMOS Cell Library Design for Testability", Liu et al., 1987, pp. 58-65.
The VLSI Design publication entitled "Integrating the Approaches to Structured Design for Testability", Gutfreund, 1983, pp. 34-42.

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