Fault-tolerant interface circuit for parallel digital bus

Details Fault-tolerant interface circuit for parallel digital bus Fault-tolerant interface circuit for parallel digital bus

1980-06-03

1981-11-03

Atkinson, Charles E.

Excavating

371 24, 371 67, G06F 1100

Patent

active

042989825

ABSTRACT:
A system for detecting and correcting a stuck condition on the bus lines of a parallel multi-channel data transmission system. The system comprises a transmitter for generating N data signal having first and second logic levels, a receiver for receiving said N signals, and a plurality of N data channels connecting said transmitter with said receiver. Each data channel comprises first and second Exclusive OR (XOR) gate means each having first and second input means and an output means. A data input signal is supplied to the first input means of said first XOR gate and the output of the second XOR gate is supplied to said receiver. Bus line means connects the output means of said first OR gate to the first input means of said second XOR gate. Logic means responds to unequal signal logic levels on the bus means and the data signal of any of said data channels to supply a first signal logic level to the second input means of all of said first and second XOR gates such that the signal logic level supplied to the first input means of said first and second XOR gate will be inverted. The logic means further responds to equal signal logic levels of said bus means and said data input signals of all of said data channels to supply a non-inverting signal logic level to the second input means of all of said first and second XOR gates.

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Sellers et al., Error Detecting Logic for Digital Computers, McGraw-Hill Book Co., 1968, pp. 85-92.

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