Programmable memory protection logic for microprocessor systems

Details Programmable memory protection logic for microprocessor systems Programmable memory protection logic for microprocessor systems

1979-08-10

1981-11-03

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 1300

Patent

active

042989345

ABSTRACT:
A microprocessor system incorporates a buffer limit address register for identifying a memory area to be protected in a microprocessor system, and an address error recognition device responsive thereto for controlling the suppression of a memory write signal in recognition of an address error.

REFERENCES:
patent: 3742458 (1973-06-01), Inoue et al.
patent: 3827029 (1974-07-01), Schlotterer et al.
patent: 4087856 (1978-05-01), Attanasio

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