Multiplying method with a round-off function and circuitry there

Details Multiplying method with a round-off function and circuitry there Multiplying method with a round-off function and circuitry there

1997-10-29

2000-01-04

Le, Thien Minh

Registers

Calculators

Motor actuated

235 63E, G06C 2300

Patent

active

06010063&

ABSTRACT:
A multiplying method with a negative/positive symmetrical round-off function and circuitry therefor are disclosed. When a product is positive, a value having a (logical) ONE at the uppermost one of bits to be rounded and ZEROs at the lower bits is rounded up. When a product is negative, a value having a (logical) ONE at the uppermost one of bits to be rounded and ZEROs at the lower bits is rounded down. This rounds off the product such that a mean accumulative error when the product is positive and a mean cumulative error when it is negative cancel each other. When a product is positive, a correction term having a ONE at the uppermost one of the bits to be rounded and ZEROs at the lower bits is applied to a subproduct adder and an adder. For a negative product, the correction term has a ZERO at the above uppermost bit and ZEROs at the lower bits.

REFERENCES:
patent: 4229800 (1980-10-01), Gregorian et al.
patent: 5444647 (1995-08-01), Komoda
patent: 5619440 (1997-04-01), Komoda
Lu, F. et al., "A Bit-Level Pipelined Implementation of a CMOS Multiplier-Accumulator Using a New Pipelined Full-Adder Cell Design", Proceedings of the Annuel International Phoenix Conference on Computers an Communications, Scottsdale, Mar. 22-24, 1989, No. 1989, Mar. 22, 1989, Institute of Electrical and Electronics Engineers, pp. 49-53.

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