Method of fabricating self-aligned lateral bipolar transistor ut

Details Method of fabricating self-aligned lateral bipolar transistor ut Method of fabricating self-aligned lateral bipolar transistor ut

1980-02-04

1981-11-03

Rutledge, L. Dewayne

Metal treatment

Compositions

Heat treating

29578, 29580, 148174, 148187, 156628, 156653, 1566591, 156662, 357 35, 357 59, 357 91, 357 92, H01L 21265, H01L 2120

Patent

active

042984025

ABSTRACT:
A surface oriented lateral bipolar transistor having a base of narrow width is fabricated by using a doped polycrystalline silicon layer as an ion implantation mask when implanting ions for the emitter and base regions. In forming the doped polysilicon mask, a first layer of dopant masking material is formed on the surface of a semiconductor substrate, a second layer of undoped polysilicon is formed over the first layer, and a third layer of dopant masking material is formed over the second layer. Portions of the second and third layers are removed and a dopant is diffused into the exposed edge portion of the second layer. The third layer and the undoped portion of the second layer are then removed thereby leaving only the doped portion of the second layer on the first layer.

REFERENCES:
patent: 3738880 (1973-06-01), Laker
patent: 3817794 (1974-06-01), Beadle et al.
patent: 4026733 (1977-05-01), Owen et al.
patent: 4026740 (1977-05-01), Owen
patent: 4057895 (1977-11-01), Ghezzo
patent: 4066473 (1978-01-01), O'Brien
patent: 4124933 (1978-11-01), Nicholas
patent: 4168999 (1979-09-01), Vora et al.
patent: 4200878 (1980-04-01), Ipri
patent: 4201603 (1980-05-01), Scott et al.

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