Semiconductor memory device

Static information storage and retrieval – Format or disposition of elements

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Details

365149, 365150, G11C 1140

Patent

active

047470780

ABSTRACT:
A semiconductor memory device in accordance with the present invention comprises an arrangement in which distances (d.sub.1, d.sub.2 and d.sub.3) between an aluminum lead )SBL1) connected to a drain of a FET of sense amplifier and an aluminum lead short-circuiting a memory cell plate formed outside the sense amplifier array are respectively equal to distances (d.sub.1, d.sub.2 and d.sub.3) between adjacent aluminum leads (SBL2 and SBL3). For the purpose of forming the above described arrangement, the shape of the lateral edge of the aluminum lead (3) facing the sense amplifier array is made the same as the shape of the lateral edge of the aluminum lead (SBL2) connected to a bit line. Thus, the capacity associated with the lead of the outermost sense amplifier in the sense amplifier array can be made almost equal to the capacity included in each lead in the sense amplifier array and at the time of reading the content stored in the capacity of the memory cell connected to the outermost bit line in the memory cell array, occurrence of an error in reading can be prevented.

REFERENCES:
patent: 3159820 (1964-12-01), Oden
patent: 3506969 (1970-04-01), Abbas
patent: 4689770 (1987-08-01), Miyamoto et al.

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