Method for dynamic testing of digital logic circuits

Details Method for dynamic testing of digital logic circuits Method for dynamic testing of digital logic circuits

1991-06-10

1996-08-27

Canney, Vincent P.

Excavating

371 251, G06F 1100

Patent

active

055508456

ABSTRACT:
A method for dynamic testing of digital logic circuits includes the application of cyclically-occurring digital signals to the inputs of a logic circuit and identifying anticipated output values in comparison to the inputs. Blank or dummy cycles are introduced after a predetermined number of test cycles, the blank or dummy cycles having the character that modifications no longer appear at the input signals. The predetermined number of test cycles is greater than or equal to 2.

REFERENCES:
patent: 4791357 (1988-12-01), Hyduke
patent: 4942576 (1990-07-01), Busack et al.
Microprocessors and Programmed Logic, Second Edition by Kenneth L. Short, .COPYRGT.1987 by Prentice-Hall Inc. pp. 20-23.
Digital Logic and Computer Design by M. Morris Mano .COPYRGT.1979 by Prentice-Hall Inc. pp. 65-68.
Antreich et al, "Zum dynamischen Testen Kombinztorischer Schaltungen" Frequenz, vol. 44, pp. 103-111.

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