Logic-circuit layout for large-scale integrated circuits

Details Logic-circuit layout for large-scale integrated circuits Logic-circuit layout for large-scale integrated circuits

1985-10-21

1988-05-24

James, Andrew J.

357 40, 357 45, 357 65, 357 70, H01L 2348, H01L 2944, H01L 2952, H01L 2960

Patent

active

047469668

ABSTRACT:
A VLSI chip has multiple annular rings of circuit cells, interspersed with annular wiring channels for interconecting the cells. Another wiring layer runs perpendicular to the rings. A central chip area contains all the I/O connections for the chip.

REFERENCES:
patent: 3558992 (1971-01-01), Heuner et al.
patent: 4413271 (1983-11-01), Gontowski, Jr. et al.
Saigo et al, "A Triple-Level Wired 24K-Gate CMOS Gate Array", IEEE Journal of Solid-State Circuits, vol. SC-20, No. 5, Oct. 1985.

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