Method for the simultaneous manufacture of fast short channel an

Details Method for the simultaneous manufacture of fast short channel an Method for the simultaneous manufacture of fast short channel an

1984-10-18

1986-01-07

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29571, 29576B, 29578, H01L 2182

Patent

active

045626383

ABSTRACT:
A manufacturing method for VLSI MOS field effect transistor circuits having digital and analog functions performed by short channel transistors and analog transistors integrated on one chip. An n-tube manufacture is performed wherein as soft as possible a field progression in front of a drain-side pn-junction of the analog transistor is achieved. This occurs by means of an additional drain implantation (curve II) with drive-in diffusion before the actual source/drain implantation (curve I) of the n-channel transistors. Both the additional implantation as well as the source/drain implantation are carried out with phosphorous ions. The dosage of the additional implantation lies one to two orders of magnitude below the dosage of the actual implantation, and the penetration depth x in the additional drive-in diffusion is about twice as great as the penetration depth x of the actual source/drain regions. The method is applied in the manufacture of VLSI CMOS circuits.

REFERENCES:
patent: 4173818 (1979-11-01), Bassous et al.
patent: 4214359 (1980-07-01), Kahng
patent: 4366613 (1983-01-01), Ogura et al.
patent: 4434543 (1984-03-01), Schwabe et al.
patent: 4459741 (1984-07-01), Schwabe et al.
1983 IEEE International Solid-State Circuits Conference; Session VIII: Modeling and Technology; "An 18V Double-Level Poly CMOS Technology for Nonvolatile Memory and Linear Applications", by Roger A. Haken et al, pp. 90 and 91.

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