Method for reducing effects of electrical noise in an analog-to-

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364724, H03M 108

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active

047468998

ABSTRACT:
Method for reducing deleterious effects of electrical noise in an analog-to-digital converter wherein both the analog and digital circuitry of the A/D converter are embodied in the same integrated circuit. The method includes sampling an analog input voltage with a first clock signal, generating a second clock signal that is delayed with respect to the first clock signal, and using the second clock signal as a clock for the digital circuitry. In accordance with another aspect of the invention, the method for reducing effects of noise in an A/D converter wherein such noise is generated by a digital decimation filter includes synchronously pipelining the arithmetic operations of the digital decimation filter.

REFERENCES:
patent: 4227185 (1980-10-01), Kronlage
patent: 4495591 (1985-01-01), Loomis, Jr.

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