Testable power-on-reset circuit

Details Testable power-on-reset circuit Testable power-on-reset circuit

1990-12-21

1993-01-19

Atkinson, Charles E.

Excavating

3072723, G01R 3128

Patent

active

051812037

ABSTRACT:
A testable power-on-reset circuit allows the reset of an electronic device without de-coupling a power signal from the electronic device. The testable power-on-reset circuit includes reset circuitry, a buffer and a buffer controller. The reset circuitry includes a reset power line on which is placed a reset power signal. The reset circuitry also includes a reset output upon which the reset circuitry places a first reset signal value responsive to the reset circuitry initially detecting the reset power signal on the reset power line and upon which the reset circuitry places a second reset signal value responsive to a period of time passing from the reset circuitry initially detecting the reset power signal on the reset power line. When it is desired to test the reset of the electronic device, the buffer controller, in response to a predetermined condition, causes the buffer to remove the reset power signal from the reset power line of the reset circuitry. The reset circuitry, in response to the removal of the reset power signal from the reset power line, removes the second reset signal value from the reset output. When the predetermined condition is removed, the buffer control causes the buffer to restore the reset power signal to the reset power line. Then, the electronic device performs a reset in response to the first reset signal value being placed on the reset output and completes the reset when the second reset signal value is placed on the reset output.

REFERENCES:
patent: 4433390 (1984-02-01), Carp et al.
patent: 4888498 (1989-12-01), Kadakia
patent: 4904883 (1990-02-01), Iino et al.
patent: 5051611 (1991-09-01), Kantz
patent: 5109163 (1992-04-01), Benhamida

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