Method for producing recessed field oxide with improved sidewall

Fishing – trapping – and vermin destroying

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437238, 437239, 437241, 437243, 427271, 427272, 4274193, 4272553, 4272557, B05D 512, B05D 132, C23C 1600

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active

047466308

ABSTRACT:
A method for producing field oxide in a silicon substrate by forming a thin oxide layer over the surface of the substrate, forming a thin nitride layer over the thin oxide layer, forming a thick oxide over the thin nitride layer, forming a thick nitride layer over the thick oxide layer; patterning all four of the layers to espose the surface of the substrate where the field oxide is to be formed; and growing the field oxide. Preferably, before the field oxide is grown, trenches are formed into the substrate so that the upper surfaces of the field oxide are substantially planar with the upper surfaces of the substrate. The thin oxide layer minimizes bird beak formation, and eases the removal of the oxide
itride/oxide
itride layers. The resultant structure is both planar and bird's beak-free, and is therefore well suited to producing VLSI components having dimensions less than 0.5 microns.

REFERENCES:
patent: 4472459 (1984-09-01), Fisher et al.
patent: 4583281 (1986-04-01), Ghezzo et al.
"Isolation Technology for Scaled MOS VLSI", by W. G. Oldham, IEDM 82; CH1832-5/82/0000-02161; 1982 IEEE; pp. 216-219.
"The Swami--A Defect Free and Near--Zero Bird's--Beak Local Oxidation Process and its Application in VLSI Technology", by K. Y. Chiu, R. Fang, J. Lin; J. L. Moll, C. Lage, S. Angelos, and R. Tillman; IEDM 82; CH1832-5/82/0000-0224; 1982 IEEE: 224-227.
"Scaling Limitations of Submicron Local Oxidation Technology", by John Jui, Paul Vande Voorde, and John Moll, IEDM 85; CH2252-5/85/0000-0392; 1985 IEEE.
"Electrical Properties of MOS Devices Made With Silo Technology", by J. Hui, T. U. Chiu, S. Wong, and W. G. Oldham; IEDM 82; CH1832-5/82/0000-0220; 1982 IEEE.
"Trench Isolation Prospects for Application in CMOS VLSI", by R. D. Rung; IEDM 84; CH2099-0/84/0000-0574; 1984 IEDM; pp. 574-577.
"CMOS Technology Using SEG Isolation Technique", by N. Endo, N. Kasai, A. Ishitani, and Y. Kurogi; IEDM 83; CH1973-7/83/0000-0031; 1983 IEEE; pp. 31-34.

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