Combined queue for invalidates and return data in multiprocessor

Details Combined queue for invalidates and return data in multiprocessor Combined queue for invalidates and return data in multiprocessor

1993-08-09

1994-07-26

Dixon, Joseph L.

Boots, shoes, and leggings

364DIG1, 3642477.239.8, 36424341, 3642545, G06F 1200, G06F 1300

Patent

active

053332962

ABSTRACT:
A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. Macroninstruction pipelining is employed (instead of microinstruction pipelining), with queuing between units of the CPU to allow flexibility in instruction execution times. A wide bandwidth is available for memory access; fetching 64-bit data blocks on each cycle. A hierarchical cache arrangement is used, increasing the likelihood of a cache hit. A writeback cache is used (instead of writethrough) and writeback is allowed to proceed even though other accesses are suppressed due to queues being full. Separate queues are provided for the return data from memory and cache invalidates, yet the order or bus transactions is maintained by a pointer arrangement. The bus protocol used by the CPU to communicate with the system bus is of the pended type, with transactions on the bus identified by an ID field specifying the originator, and arbitration for bus grant goes one simultaneously with address/data transactions on the bus.

REFERENCES:
patent: 4543626 (1985-09-01), Bean et al.
patent: 4600986 (1986-07-01), Scheuneman et al.
patent: 4674032 (1987-06-01), Michaelson
patent: 4855904 (1989-08-01), Daberkow et al.
patent: 4949301 (1990-08-01), Joshi et al.
patent: 4995401 (1991-02-01), Hetherington et al.
patent: 5019965 (1991-05-01), Webb, Jr. et al.
patent: 5023828 (1991-06-01), Grundmann et al.
patent: 5058006 (1991-10-01), Durdan et al.
patent: 5101486 (1992-03-01), Okamoto
patent: 5107457 (1992-04-01), Hayes et al.
patent: 5109495 (1992-04-01), Fite et al.
patent: 5133062 (1992-07-01), Joshi et al.

Affiliated with

Also associated with

Rating

Combined queue for invalidates and return data in multiprocessor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Combined queue for invalidates and return data in multiprocessor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Combined queue for invalidates and return data in multiprocessor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1058028