Signal conditioning circuit

Communications: radio wave antennas – Antennas – Balanced doublet - centerfed

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Details

324 78D, 325325, 328136, G01S 144

Patent

active

039952720

ABSTRACT:
A signal conditioning circuit for a fixed rise time, variable amplitude receiving system (TACAN) that digitizes the time of arrival and samples the pulse amplitude at the receiver's last intermediate frequency (IF) stage before video detection. The time of arrival measurement is performed by counting a fixed number of successive threshold crossings of the IF carrier, utilizing a pair of comparators having two inputs each. One input of each comparator is coupled to the IF stage. The other input of each comparator is coupled to a point of reference potential, one comparator being referenced to ground and the other being coupled to a small positive threshold voltage level. The output of the grounded comparator is delayed, and the delayed output is used as a clock signal to the remaining circuitry. The output of the threshold comparator provides data pulses, one data pulse being generated each time that the IF signal goes above the threshold value. The data pulses, along with the clock pulses, are applied to an up down shift register which acts as a digital flywheel. The output of the digital fly-wheel enables and disables a counter.
Two signal conditioning circuits are described, one which extracts time information, and one which extracts amplitude information from a fixed rise time, pulse-amplitude modulated carrier as is found in a typical TACAN receiver at the last intermediate frequency (IF) stage. The time of arrival of the leading edge 50% voltage point is determined in real time with virtually zero delay, and therefore does not rely on conventional approaches which must first wait until the full unknown amplitude of the pulse is determined before a 50% detector is enabled. The technique is based on the fact that there are a fixed number of cycles of IF carrier under the leading edge of the pulse regardless of its amplitude and that therefore the 50% voltage point is determined by counting in an electronic counter a fixed number of "consecutive" cycles that exceed a pre-determined noise threshold as determined by a comparator set at that threshold. The technique operates on the signal one stage before conventional video detection. Erroneous false alarm and false dismissal threshold crossings are rejected by a digital up-down shift register which acts as a fly-wheel. The peak amplitude of the IF pulse-amplitude modulated carrier is detected, sampled, amplified, and buffered in one efficient circuit. The detection function is performed by charging a capacitor, which is isolated from the raw IF by a differential amplifier stage, up to a voltage proportional to each successive carrier cycle peak by a closed loop means. Since the capacitor can only charge in one direction, it charges up to a voltage proportional to the most positive peak of the pulse-amplitude modulated carrier, with a fixed amount of rate limiting for noise immunity. Two logic signals, a Track/Hold command and a Dump command are used to respectively hold the peak amplitude for subsequent analog to digital conversion and digital signal processing, and to reset the detector prior to encoding another pulse.

REFERENCES:
patent: 3714657 (1973-01-01), Lapeyre
patent: 3836864 (1974-09-01), Jezo
patent: 3852671 (1974-12-01), Risley
patent: 3921076 (1975-11-01), Currie

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