DMA controller having jump function

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Details

36424231, 3642423, G06F 1200

Patent

active

053332903

ABSTRACT:
A direct memory access (DMA); controller for controlling data transfer between a memory and an input/output (I/O) device comprises an address counter for counting an address to be supplied to the memory, and a read/write controller for controlling a read/write operation between the memory and the I/O device. A jump start address register is provided to hold a jump start address, and an address comparator compares a content of the address counter with a content of the jump start address register. When the address comparator detects consistence between the content of the address counter and the content of the jump start address register, the read/write controller operates to stop the read/write operation between the memory and the I/O device.

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patent: 4864533 (1989-09-01), Hanada
patent: 4924410 (1990-05-01), Hamada
patent: 4980828 (1990-12-01), Kapcio
patent: 5109501 (1992-04-01), Kaneko et al.
patent: 5291582 (1994-03-01), Drako et al.

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