Computer bus having page mode memory access

Details Computer bus having page mode memory access Computer bus having page mode memory access

1987-09-17

1990-04-17

Zache, Raulfe B.

Boots, shoes, and leggings

364940, 3649401, 3649402, 3649591, 364964, 364952, 3649521, 364957, 3649571, 3649649, 364968, 364943, 36494343, 364928, 3649272, 36493701, 3649428, 364942, G06F 1200, G06F 1300

Patent

active

049186450

ABSTRACT:
Method and apparatus are disclosed for use in a digital computer system having a system bus for interconnecting together various agents. A page mode type of memory access provides for the rapid transmission of a block of data across the bus. Blocked refresh circuitry is also employed which disables, if possible, the burst refresh of the memory until a data transfer is completed. A local processor upon an agent having a memory controlled in such manner is provided with a high priority signal line for overriding a current bus transfer for gaining access to the memory. During such a high priority access the blocked refresh circuitry operates in a manner somewhat similar to its operation during the sequential bus transfer, however fewer rows are refreshed during the burst refresh.

REFERENCES:
patent: 4691303 (1987-09-01), Churchward et al.
patent: 4694454 (1987-09-01), Matsuura
patent: 4700330 (1987-10-01), Altman et al.
patent: 4701843 (1987-10-01), Cohen
patent: 4716551 (1987-12-01), Inagaki
patent: 4754425 (1988-06-01), Bhadriraju
"High Performance 32-Bit Bus Standard P1296", (Unapproved Draft), The institute of Electrical and Electronics Engineers, Inc., Jun. 20, 1986.
"Dame-II Chip", NCR Corporation Preliminary Functional Specification 530-0006100, Jul., 1986.
"Boss Chip", NRC Corporation Functional Specification 530-0006112, Feb., 1987.

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