Boots – shoes – and leggings
Patent
1988-08-01
1990-04-17
Zache, Raulfe B.
Boots, shoes, and leggings
364242, 3642431, 364246, 3642463, 364254, 3642544, G06F 1206
Patent
active
049186000
ABSTRACT:
Conflict-free vector access of any constant stride is made by preselecting a storage scheme for each vector based on the accessing patterns to be used with that vector. A respective storage scheme for each vector, for example, is selected to provide conflict-free access for a predetermined stride S. The respective storage scheme involves a rotation or permutation of an addressed row of corresponding memory locations in N parallel modules in main memory. The amount of rotation or permutation is a predetermined function of the predetermined stride S and the row address. The rotation is performed by modulo-N addition, or the permutation is performed by a set of exclusive-OR gates. For a system in which N is a power of 2 such that n=log.sub.2 N, the predetermined stride S is factored into an odd component and an even component that is a power of 2. The factorization is easily performed by a shift and count procedure, a shifter and counter, or a priority encoder. The amount of rotation or permutation is a predetermined function of the even component and the row address, and is preferably obtained by selecting a field of the row address in accordance with the maximum of s and n, and masking the selected field with a mask generated from the minimum of s and n.
REFERENCES:
patent: 4370732 (1983-01-01), Kogge
patent: 4400768 (1983-08-01), Tomlinson
patent: 4435765 (1984-03-01), Uchida et al.
patent: 4731724 (1988-03-01), Michel et al.
Paul Budnik and David J. Kuck, "The Organization and Use of Parallel Memories," IEEE Transactions on Computers, C-20(12), pp. 1566-1569, (Dec. 1971).
R. C. Swanson, "Interconnections for Parallel Memories to Unscramble p-Ordered Vectors," IEEE Transactions on Computers, C-23, pp. 1105-1115, (Nov. 1974).
Duncan H. Lawrie, "Access and Alignment of Data in an Array Processor," IEEE Transactions on Computers, C-24(12), pp. 1145-1155, (Dec. 1975).
K. E. Batcher, "The Multidimensional Access Memory in STARAN," IEEE Transactions on Computers, C-26, pp. 174-177, (Feb. 1977).
Duncan H. Lawrie and Chandra R. Vora, "The Prime Memory System for Array Access," IEEE Transactions on Computers, C-31(5), pp. 435-442, (May 1982).
J. M. Frailong, W. Jalby, and J. Lenfant, "XOR-Schemes: A Flexible Data Organization in Parallel Memories," 1985 International Conference on Parallel Processing, pp. 276-283, (1985).
Abhiram G. Ranade, "Interconnection Networks and Parallel Memory Organizations for Array Processing," Proceedings of the 1985 International Conference on Parallel Processing, pp. 41-47, (Aug. 1985).
Wilfried Oed and Otto Lange, "On the Effective Bandwidth of Interleaved Memories in Vector Processing Systems," IEEE Transactions on Computers, C-34(10), pp. 949-957, (Oct. 1985).
D. T. Harper, III and J. R. Jump, "Vector Access Performance in Parallel Memories Using a Skewed Storage Scheme," IEEE Transactions on Computers, C-36(12), pp. 1440-1449, (Dec. 1987).
Alan Norton and Evelyn Melton, "A Class of Boolean Linear Transformations for Conflict-Free Power-of-Two Stride Access," Proceedings of the 1987 International Conference on Parallel Processing, pp. 247-254, (1987).
Harper, III David T.
Linebarger Darel A.
Board of Regents University of Texas System
Zache Raulfe B.
LandOfFree
Dynamic address mapping for conflict-free vector access does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dynamic address mapping for conflict-free vector access, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamic address mapping for conflict-free vector access will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1057184