Excavating
Patent
1990-01-17
1993-09-21
Dixon, Joseph L.
Excavating
395725, 371 12, 371 13, G06F 938, G06F 1100, G06F 1130
Patent
active
052476286
ABSTRACT:
A data processing system for executing a sequence of instructions. The data processing system includes several processors each for executing instructions. Also included is a dispatching apparatus for dispatching each of the instructions to one of the processors. Control circuitry is included for directing the concurrent execution of the dispatched instructions in the processors irrespective of the location of the instructions in the sequence. The control circuitry includes the capability to receive an instruction interrupt signal. The control circuitry then determines which instruction generated the instruction interrupt. Upon this determination, the control circuitry resets the processors and the dispatching apparatus to the state that existed when the instruction that generated the instruction interrupt was earlier executed in order to re-execute the instruction that caused the interrupt signal in accordance with its location in the instruction sequence.
REFERENCES:
patent: 3736566 (1973-05-01), Anderson et al.
patent: 4044337 (1977-08-01), Hicks et al.
patent: 4110822 (1978-08-01), Porter et al.
patent: 4200927 (1980-04-01), Hughes et al.
patent: 4205370 (1980-03-01), Hirtle
patent: 4471433 (1984-09-01), Matsumoto et al.
patent: 4477872 (1984-10-01), Losq et al.
patent: 4507732 (1985-03-01), Catiller et al.
patent: 4524415 (1985-06-01), Mills, Jr. et al.
patent: 4532589 (1985-07-01), Shintani et al.
patent: 4541047 (1985-09-01), Wada et al.
patent: 4594655 (1986-06-01), Hao et al.
patent: 4594661 (1986-06-01), Moore et al.
patent: 4626989 (1986-12-01), Torii
patent: 4644465 (1987-02-01), Imamura
patent: 4709324 (1987-11-01), Kloker
patent: 4740969 (1988-04-01), Fremont et al.
patent: 4745547 (1988-05-01), Buchholz et al.
patent: 4751639 (1988-06-01), Cororan et al.
patent: 4763294 (1988-08-01), Fong
patent: 4777587 (1988-10-01), Case et al.
patent: 4782441 (1988-11-01), Inagami et al.
patent: 4791555 (1988-12-01), Garcia et al.
patent: 4797816 (1989-01-01), Uchiyama et al.
patent: 4805095 (1989-02-01), Armstrong et al.
patent: 4809159 (1989-02-01), Sowa
patent: 4811211 (1989-03-01), Sandman et al.
patent: 4811215 (1989-03-01), Smith
patent: 4814978 (1989-03-01), Dennis
patent: 4875160 (1989-10-01), Brown, III
patent: 4893234 (1990-01-01), Davidson et al.
patent: 4956800 (1990-09-01), Kametani
patent: 4965882 (1990-10-01), Barabash et al.
D. C. Tjon-Pian-Gi, "Vector-Register Rename Mechanism", IBM Technical Disclosure Bulletin, vol. 25, No. 1, Jun., 1982 pp. 86-87.
R. Cytron, "Doacross: Beyond Vectorization for Multiprocessors" (Extended Abstract), 1986 IEEE Int. Conf. on Parallel Processing pp. 836-844.
P. Tang et al., "Processor Self-Scheduling for Multiple-Nested Parallel Loops", Proc. 1986 Int. Conf. Parallel Proc. Aug. 1986, pp. 528-535.
IBM Technical Disclosure Bulletin, vol. 23, No. 11, Apr. 1981, p. 5271, "Instruction Nullification by Saving and Restoring Architected Data".
IBM Technical Disclosure Bulletin, vol. 17, No. 8, Jan., 1975, pp. 2239-2242, "Instruction Retry Mechanism for a Computer".
IBM Technical Disclosure Bulletin, vol. 15, No. 5, Oct., 1972, pp. 1576-1577, "Emulator Instruction Retry".
IBM Technical Disclosure Bulletin, vol. 13, No. 12, May, 1971, pp. 3855-3856, "Instruction Retry".
IBM Technical Disclosure Bulletin, vol. 25, No. 10, Mar., 1983, p. 5300, "Instruction Retry Mechanism for a Multicroprocessor System".
IBM Technical Disclosure Bulletin, vol. 11, No 11, Apr., 1969, pp. 1409-1410, "Error Retry Implementation".
IBM Technical Disclosure Bulletin, vol. 22, No. 5. Oct., 1979, pp. 1809-1810, "Restoration of Arrays Containing Bad Parity".
IBM Technical Disclosure Bulletin, vol. 22, No. 5, Oct., 1979, pp. 1811-1812, "Microcode Control for Instruction Retry".
Dixon Joseph L.
Drake Paul S.
International Business Machines - Corporation
Tyson Thomas E.
Whitfield Michael A.
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