System for limiting change in bus clock frequency to duration of

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Details

395180, 395821, 395500, G06F 114

Patent

active

055465676

ABSTRACT:
A computer system includes a program executing section for executing a program, an instruction generating section for generating a frequency change instruction in response to the execution of the program, and a changing section for changing the frequency of an operation clock of a system bus in reponse to the frequency change instruction. The frequency of the operation clock of the system bus is changed when an interface having a low operation rate is accessed. Therefore, an average speed of the system can remain high.

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