Compact CMOS device structure

Details Compact CMOS device structure Compact CMOS device structure

1988-10-31

1990-04-17

Edlow, Martin H.

357 59, 357 236, 357 2311, 357 41, H01L 2702

Patent

active

049185101

ABSTRACT:
A compact CMOS structure and method for fabricating the structure are disclosed. In one embodiment of the invention the structure includes a P-type surface region in a silicon substrate surrounded by a field oxide which extends, at least in part, above the surface of the substrate. A polycrystalline silicon sidewall frame is formed at the sidewall of the field oxide and a gate insulator is formed over both the polycrystalline silicon frame and the silicon surface region. A common gate electrode is formed which traverses the frame and the surface region. P-type source and drain regions are formed in the polycrystalline silicon frame on opposite sides of the gate electrode and N-type source and drain regions are formed in the surface region on opposite sides of the gate electrode.

REFERENCES:
patent: 4370669 (1983-01-01), Donley
patent: 4404579 (1983-09-01), Leuschner
patent: 4651408 (1987-03-01), MacElwee
patent: 4654121 (1987-03-01), Miller et al.
patent: 4710897 (1987-12-01), Masuoka
patent: 4771323 (1988-09-01), Saski
patent: 4799097 (1989-01-01), Szluk et al.

Affiliated with

Also associated with

Rating

Compact CMOS device structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Compact CMOS device structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Compact CMOS device structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1056454