Reduced mask DRAM process

Details Reduced mask DRAM process Reduced mask DRAM process

1995-06-28

1996-08-27

Tsai, H. Jey

Fishing, trapping, and vermin destroying

437 60, 437919, 437 56, H01L 2170, H01L 2700

Patent

active

055500781

ABSTRACT:
A process for fabricating stacked capacitor DRAM devices has been developed in which self aligned storage node contact structures, as well as bit line contact structures, are featured. A split polysilicon process has also been used to allow maskless source and drain ion implantation processing to be realized, thus reducing the number of photolithographic steps. A dual dielectric, interlevel insulator, is used to eliminate leakage between metal levels.

REFERENCES:
patent: 5134085 (1992-07-01), Gilgen et al.
patent: 5252504 (1993-10-01), Lowrey et al.
patent: 5406103 (1995-04-01), Ogawa
patent: 5496758 (1996-03-01), Ema

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