Method for manufacturing an EEPROM cell

Details Method for manufacturing an EEPROM cell Method for manufacturing an EEPROM cell

1995-07-07

1996-08-27

Tsai, H. Jey

Fishing, trapping, and vermin destroying

437 49, 437 52, H01L 21265

Patent

active

055500730

ABSTRACT:
A method for manufacturing a full-feature EEPROM cell is provided, which includes the steps of forming a gate isolating layer and a conductive layer on a predetermined region of the substrate to be a selective gate of the selective-gate transistor, and thereby defining a channel region; forming a masking layer on the selective gate and the substrate; forming sidewall spacers beside the selective gate and on the masking layer, and defining a channel region of the stacked-gate transistor using the sidewall spacer, forming a stacked-gate layer on the selective gate and the channel region of the stacked-gate transistor, and implanting a second type of dopant into the substrate to form heavily doped regions by using the selective gate and the stacked gate as masks, so that each of the lightly doped regions, which may combine with one of the heavily doped regions to form a LDD structure, respectively forms sources and drains of the selective-gate transistor and the stacked-gate transistor.

REFERENCES:
patent: 4988635 (1991-01-01), Ajika et al.

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