Method for fabricating high-voltage complementary metal-oxide-se

Details Method for fabricating high-voltage complementary metal-oxide-se Method for fabricating high-voltage complementary metal-oxide-se

1995-09-29

1996-08-27

Bowers, Jr., Charles L.

Fishing, trapping, and vermin destroying

437 41, 437 57, H01L 218238

Patent

active

055500641

ABSTRACT:
A method for fabricating high-voltage CMOS transistors comprises the steps of: forming a well of a second conductivity type and two lightly-doped diffusion regions of the second conductivity type in a silicon substrate of a first conductivity type; forming a plurality of shielding blocks over the silicon substrate to define source/drain and gate regions; implanting impurities of the first conductivity type in the diffusion regions of the first conductivity type to form drift regions of the first conductivity type therein; implanting impurities of the second conductivity type in the diffusion regions of the second conductivity type to form drift regions of the second conductivity type therein; forming field oxide layers between the shielding blocks over the silicon substrate; removing the shielding blocks; forming gate oxide layers on the exposed surfaces of the silicon substrate and the well respectively; forming gate electrodes over the gate oxide layers; and forming source/drain implanted regions of the first conductivity type in the well and forming source/drain implanted regions of the second conductivity in the silicon substrate.

REFERENCES:
patent: 4818719 (1989-04-01), Yeh et al.
patent: 5376568 (1994-12-01), Yang
patent: 5382820 (1995-01-01), Yang et al.
patent: 5393679 (1995-02-01), Yang
patent: 5424226 (1995-06-01), Vo et al.
patent: 5486482 (1996-01-01), Yang

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