TTL output driver gate configuration

Details TTL output driver gate configuration TTL output driver gate configuration

1988-06-15

1990-04-17

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

357 2314, 307443, 307450, 307451, 307546, 307263, 307572, H03K 301, H03K 1716, H03K 19094

Patent

active

049183320

ABSTRACT:
A TTL output driver gate configuration which has reduced voltage spikes on internal power supply potential and ground potential nodes includes a P-channel pull-up transistor (P1), an N-channel pull-down transistor (N1), a NAND logic gate (14), a NOR logic gate (16), a first positive feedback amplifier circuit (18), and a second positive feedback amplifier circuit (20). The pull-up transistor (P1) and the pull-down transistor (N1) have gates which are made serpentine. The reduction of voltage spikes is achieved by slowing down the turn-on times of the pull-up and pull-down transistors during transitions due to the distributed resistances and capacitances of the polysilicon material used to form the serpentine gates thereof. The first and second positive feedback amplifier circuits (18, 20) are used to pull the undriven gate ends of the respective transistors all the way to negative and positive supply potentials so as to facilitate transitions at an output node.

REFERENCES:
patent: 4602170 (1986-07-01), Bertin
patent: 4771195 (1988-09-01), Stein

Affiliated with

Also associated with

Rating

TTL output driver gate configuration does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with TTL output driver gate configuration, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and TTL output driver gate configuration will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1054789