Output driver circuit having reduced VSS/VDD voltage fluctuation

Details Output driver circuit having reduced VSS/VDD voltage fluctuation Output driver circuit having reduced VSS/VDD voltage fluctuation

1991-09-16

1994-07-26

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307475, H03K 1716, H03K 190948

Patent

active

053329325

ABSTRACT:
An output buffer driver circuit which significantly reduces the effects of voltage fluctuations in the upper and lower power supply potentials on an output signal includes a first pull-up circuit (44), a second pull-up circuit (46), a first pull-down circuit (48), a second pull-down circuit (50), a delay circuit (52), and control circuit (54). The first pull-up circuit (44) is coupled between a noisy upper power supply potential (VDDN) and output terminal (43). The second pull-up circuit (46) is coupled between a quiet upper power supply potential (VDDQ) and the output terminal. The first pull-down circuit (48) is coupled between noisy lower power supply potential (VSSN) and the output terminal. The second pull-down circuit (50) is coupled between a quiet lower power supply potential (VSSQ) and the output terminal. The second pull-up circuit (46) is delayed in its turn-on until the first pull-up circuit (44) is being turned-off when the output terminal is making the low-to-high transition so as to isolate the noisy upper power supply potential from the output terminal. Similarly, the second pull-down circuit (50) is delayed in its turn-on until the first pull-down circuit (48) is being turned-off when the output terminal is making the high-to-low transition so as to isolate the noisy lower power supply potential from the output terminal.

REFERENCES:
patent: 4731553 (1988-03-01), Van Lehn et al.
patent: 4928023 (1990-05-01), Marshall
Chen, John Y.; "CMOS Devices and Technology for VLSI"; .COPYRGT.1990 by Prentice Hall; Englewood Ciffs, N.J.; pp. 104-105.

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