Semiconductor memory device having decoder

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

Patent

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Details

365233, 36523008, G11C 800

Patent

active

055463525

ABSTRACT:
In the present invention, a row address processing circuit and a column address processing circuit operate in synchronism with an externally applied synchronous signal in a semiconductor memory device. The row address processing circuit and the column address processing circuit each include an address buffer and a decoder. The address buffer or decoder operates in synchronism with the synchronous signal.

REFERENCES:
patent: 5054002 (1991-10-01), Ninomiya et al.
patent: 5327390 (1994-07-01), Takasugi

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