Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Utilizing three or more electrode solid-state device
Patent
1994-11-07
1996-08-13
Nelms, David C.
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Utilizing three or more electrode solid-state device
327483, 327484, 327108, 327576, H03K 17687, H03K 1760, H03K 300
Patent
active
055460437
DESCRIPTION:
BRIEF SUMMARY
This application is a filing under U.S.C. 371 of PCT/DE93/00386.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a circuit arrangement for driving an MOS field-effect transistor as a power switching element in a DC/DC voltage converter operating on the chopper principle, the source connection of the MOS field-effect transistor assuming a potential which differs as a function of its switching state.
2. Description of the Related Art
In present-day portable personal computers, electrical power is supplied to both the electronics and the disk drives via switched-mode regulators which are known per se. These regulators have a high efficiency. However, the forward-voltage loss of a switched-mode regulator having a bipolar switching stage is approximately 1 volt. In the case of a low input voltage of approximately +6 V and a desired output voltage of +5 V, these losses are relatively high. These losses can be greatly reduced by the use of an MOS field-effect transistor as a voltage interrupter with a low switched-on resistance.
A gate driver, for example, is required for driving low-resistance n-channel field-effect transistors, which gate driver produces gate-source voltages of
If it is intended to implement an input voltage range of UE=+5.5 V to +15 V, the source voltage of the MOS field-effect transistor changes, as a result of it switching, for example from
In the case of an input voltage of UE=+15 V, the switched-on gate voltage is
In the case of an input voltage of UE=+5.5 V, the switched-on gate voltage is V=UGmax+UEmin
The gate control voltage for the selected input voltage range from UE=+5.5 V to 15 V must therefore lie between
The voltage of normal integrated gate drivers is limited to Umax=20 V and they have a disadvantageously high internal current consumption. This is a result of the fast charge reversal of internal capacitances with a large voltage change and steep edge gradient at the output. A steep edge gradient is important in order to keep the switching losses low in the MOS field-effect transistor.
A circuit arrangement for driving an MOS field-effect transistor within a DC/DC converter is disclosed, for example, in U.S. Pat. No. 4,859,927. This operates with a complementary transistor stage, via which the MOS field-effect transistor is driven. The complementary transistor stage is in this case connected on at least one side to a supply voltage. The base connections of the complementary transistors are connected to a control circuit which drives the complementary transistors as a function of a predetermined output voltage from the DC/DC voltage converter.
The document U.S. Pat. No. 3,654,490 discloses a further circuit arrangement for driving an MOS field-effect transistor having a pair of complementary transistors. In the case of this circuit arrangement, the bases of the complementary transistors are not directly connected to one another, but they are driven separately via in-phase control signals. In this case, a phase reversing transistor is assigned to one of the two complementary transistors.
As a rule, switched-mode regulator chips have a normal relative switched-on duration of 90%. However, a switched-on duration of 100% would be desirable. The phase reversing transistor mentioned above admittedly has a storage time by means of which the switched-on duration of the associated circuit arrangement can be influenced. However, no further measures are specified in order actually to ensure a 100% switched-on duration.
SUMMARY OF THE INVENTION
An object of the invention is thus to provide a circuit arrangement of the type mentioned initially, by means of which a 100% switched-on duration can be ensured.
This and other objects and advantages are achieved according to the invention by the circuit arrangement for driving an MOS field-effect transistor as a power switching element in a DC/DC voltage converter operating on the chopper principle, having a pair of complementary transistors formed from two further transistors whose bases are driven with in-phase
REFERENCES:
patent: 3654490 (1972-04-01), Kan
patent: 4859927 (1989-08-01), Meijer
patent: 4940906 (1990-07-01), Gulczynski
patent: 5352932 (1994-10-01), Tihanyi
patent: 5371418 (1994-12-01), Leipold et al.
patent: 5376831 (1994-12-01), Chen
patent: 5397878 (1995-05-01), Chen
patent: 5416361 (1995-05-01), John et al.
Japanese Abstract, T. Nagafune, "Driving Circuit for Field Effect Transistor", vol. 5 No. 181 (E-83) (853), Nov. 20, 1981, JP, A56-109037.
B. Roehr, "VMOS Transistors Interface ICs to High Power Loads", 8167 Computer Design, vol. 20 (1981) Nov., No. 11, Winchester, Mass, USA, pp. 233-240.
Nelms David C.
Phan Trong
Siemens Nixdorf Informationssysteme Aktiengesellschaft
LandOfFree
Circuit arrangement for driving an MOS field-effect transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit arrangement for driving an MOS field-effect transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit arrangement for driving an MOS field-effect transistor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1051257