Patent
1991-06-27
1993-06-15
Richardson, Robert L.
G06F 1342
Patent
active
052206602
ABSTRACT:
A parallel data processing apparatus including a plurality of processors, a pair of signal paths are provided for each processor, one signal path of each pair being used for supplying a predetermined signal to the processor, and the second signal path being used for returning the signal from the processor to a predetermined position common to all of the processors. Each of the above signal paths include a variable delay unit. The apparatus further includes a delay measuring unit for measuring the time elapsing while the signal is propagated from the above predetermined position to a corresponding processor and then returned from the processor to the above predetermined position through each pair of signal paths. Further the apparatus includes a delay adjusting unit for adjusting the delays caused by the variable delay units in all of the signal paths. The delay adjustment are based on the results of a measurement by the delay measuring unit, so that the time elapsing while the signal is propagated from the predetermined position to the plurality of processors, through the respective signal paths for supplying the signal to the processors, are equal.
REFERENCES:
patent: 4805196 (1989-02-01), Cooperman et al.
patent: 5041966 (1991-08-01), Nakai et al.
patent: 5086500 (1992-02-01), Greub
Iciki Hiroki
Kato Hideki
Masumoto Daiki
Yoshizawa Hideki
Fujitsu Limited
Richardson Robert L.
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