Recoded iterative multiplier

Boots – shoes – and leggings

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G06F 752

Patent

active

052205258

ABSTRACT:
A recorded iterative multiplier (20) performs an unsigned multiplication operation quickly and with a minimal amount of added circuitry. Multiplier (20) includes a Modified Booth recoder (34) and a plurality of multiplexors (24, 26, 28, 30, and 32) to provide a plurality of partial products. An additional partial product typically generated during a first iteration of the multiplication operation is provided to a multiplexor (44) and a remaining portion of partial products are provided to a summation tree (40) having a symmetrical circuit layout. [Multiplexor (44) stores the additional partial product until summation tree (40) has processed the remaining partial products to provide a first sum.] When summation tree (40) has processed the remaining partial products to provide a first sum, multiplexor (44) provides the additional partial product to a carry save adder (42). The first sum is added to the additional partial product in [a carry-save] adder (42) to provide a first portion of a product. During a second iteration of the multiplication operation, an additional partial product is not generated, and summation tree (40) provides the second portion of the multiplication product. The first and second portions are then summed in carry-save adder (42) to provide the multiplication product.

REFERENCES:
patent: 4546446 (1985-10-01), Machida
patent: 4575812 (1986-03-01), Kloker et al.
patent: 4752905 (1988-06-01), Nakagawa et al.
patent: 4831577 (1989-05-01), Wei et al.
patent: 4965762 (1990-10-01), Williams
patent: 5001661 (1991-03-01), Corleto et al.
IBM Tech. Disclosure Bull., vol. 27, No. 11, Apr. 1985, pp. 6624-6632, "Improved Approach to the Use of Booth's Multiplication Algorithm".
"High-Speed Monolithic Multipliers for Real-Time Digital Signal Processing" written by Shlomo Waser and published in IEEE Computer in Oct. 1978, pp. 19-29.

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