N-pi phase/frequency detector

Pulse or digital communications – Repeaters – Testing

Patent

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Details

375119, 328133, H04L 2714

Patent

active

050273736

ABSTRACT:
A digital phase/frequency detector circuit in a phase locked loop comprises multiple bistable devices which are clocked up and down respectively by input and references digital signals to generate square waves. The duty ratio corresponds to the phase/frequency difference and sweeps repetitively between minimum and maximum values as the phase/frequency difference changes monotonically. The square waves are combined logically and additively in the output. The output is integrated to obtain an every increasing output over many cycles of the phase/frequency difference until the maximum is reached depending on the number of bistable devices which are used. Added circuitry is used to avoid coincidence problems in the clocking input and reference digital signals, to minimize resultant irregularities, and hold the bistable devices at maximum or minimum, as appropriate, until the direction of phase/frequency difference reverses. At either maximum or minimum a sawtooth waveform exists of one magnitude of value out of many magnitudes of value between maximum and minimum. The many magnitudes depend on the number of bistable devices.

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J. Eijeselendoorn and R. C. Dvlk, "Improved Phase Locked Loop Performance with Adaptive Phase Comparators", IEEE Transactions on Aerospace and Electronic Systems, vol. AES-18, No. 3, May 1982.

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