Sense amplifier pulldown circuit for minimizing ground noise at

Details Sense amplifier pulldown circuit for minimizing ground noise at Sense amplifier pulldown circuit for minimizing ground noise at

1992-03-06

1993-06-15

Wambach, Margaret R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307491, 3075421, 307572, 307263, 307605, 3072968, H03F 345, G06G 710

Patent

active

052202216

ABSTRACT:
A pulldown circuit for a sense amplifier includes an output node for coupling to a common node of one or more sense amplifiers in a DRAM. The drain of an N-channel pulldown transistor is coupled to the output node. Additional pulldown circuitry includes an inverter, a P-channel transistor, and a bias circuit coupled to the supply voltage for providing a gate signal to the gate of the N-channel pulldown transistor. The slope of the gate signal is substantially insensitive to the value of the power supply voltage, thus changing the rate at which the common node is discharged to the enabling ground level. Since the rate of discharge is substantially the same at higher power supply voltages, the instantaneous current is substantially the same, which in turn prevents the internal ground lines from developing an additional undesirable ground voltage increase.

REFERENCES:
patent: 4000413 (1976-12-01), Wong et al.
patent: 4551641 (1985-11-01), Pelley, III
patent: 4791613 (1988-12-01), Hardee
patent: 5042011 (1991-08-01), Casper et al.
patent: 5045772 (1991-09-01), Nishiwaki et al.
patent: 5065055 (1991-11-01), Reed
patent: 5138201 (1992-08-01), Ohbayashi et al.
patent: 5140199 (1992-08-01), Seo
"A 4096-Bit High-Speed Emitter-Coupled Logic (ECL) Compatible Random Access Memory" Ebel et al., IEEE Journal of Solid-State Circuits, vol. SC10, No. 5, Oct. 1975.

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