Direct memory access controller using prioritized interrupts for

Details Direct memory access controller using prioritized interrupts for Direct memory access controller using prioritized interrupts for

1989-12-27

1991-12-10

Shaw, Dale M.

Boots, shoes, and leggings

3642405, 3642407, 3642414, 3642415, 36424231, 364DIG1, G06F 1334

Patent

active

050723650

ABSTRACT:
A data processing system having a direct memory access controller (DMAC) which can be interrupted with a prioritized signal to vary bus mastership of a communication bus in the system. A prioritized interrupt signal is sent to a CPU when the DMAC has bus mastership. The CPU only informs the DMAC of the highest priority cumulative interrupt priority. With the use of a mask value, the interrupt may be selectively screened by the DMAC so that selective interrupts may remove bus mastership from the DMAC.

REFERENCES:
patent: 4023143 (1977-05-01), Braunstein
patent: 4035780 (1977-07-01), Kristick
patent: 4067059 (1978-01-01), Perchak
patent: 4200912 (1980-04-01), Harrington et al.
patent: 4240140 (1980-12-01), Stafford et al.
patent: 4257095 (1981-03-01), Nadir
patent: 4443848 (1984-04-01), Gehman
patent: 4755938 (1988-07-01), Takahashi
patent: 4953103 (1990-08-01), Suzuki

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