1990-12-04
1991-12-10
Prenty, Mark
357 234, 357 237, 357 55, H01L 2702, H01L 2978, H01L 2701, H01L 2906
Patent
active
050722760
ABSTRACT:
A new class of CMOS integrated circuits, wherein the PMOS and NMOS devices are both configured as vertical transistors. One trench can contain a PMOS device, an NMOS device, and a gate which is coupled to control both the PMOS device and the NMOS device. Latchup problems do not arise, and n+ to p+ spacing rules are not required.
REFERENCES:
patent: 4554572 (1985-11-01), Chatterjee
patent: 4566025 (1986-01-01), Jastrzebski et al.
patent: 4566914 (1986-01-01), Hall
patent: 4660062 (1987-04-01), Nishizawa et al.
patent: 4670768 (1987-06-01), Sunami et al.
patent: 4713678 (1987-12-01), Womack et al.
patent: 4740826 (1988-04-01), Chatterjee
Mahant-Shetti Shivaling S.
Malhi Satwinder S.
Sundaresan Ravishankar
Comfort James T.
Merrett N. Rhys
Prenty Mark
Sharp Melvin
Texas Instruments Incorporated
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