Semiconductor integrated circuit device in which a semiconductor

Details Semiconductor integrated circuit device in which a semiconductor Semiconductor integrated circuit device in which a semiconductor

1989-09-13

1991-06-25

LaRoche, Eugene R.

357 65, H01L 2348

Patent

active

050271881

ABSTRACT:
A multi-layered structure of wirings on a semiconductor substrate has been employed in conjuction with the increase in the integration density of semiconductor integrated circuit devices. In the invention, dummy patterns made of the same material as an Al wiring layer for compensating for any step or level gradation are disposed in the regions below bump electrodes and in the proximity thereof in order to reduce any defects inherent to a multi-layered structure that occur in CCB bump electrodes formed on the multi-layered wirings and at pads as the base layer of the former.

REFERENCES:
patent: 4316208 (1982-02-01), Kobayashi et al
L. F. Miller, Controlled Collapse Reflow Chip Joining, May 1969, pp. 239-249.

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