Polycide gate FET with salicide

Details Polycide gate FET with salicide Polycide gate FET with salicide

1990-03-30

1991-06-25

Prenty, Mark

357 67, 357 71, 357 239, H01L 2904, H01L 2348, H01L 2946, H01L 2906

Patent

active

050271857

ABSTRACT:
A process for forming a field-effect-transistor structure upon a silicon substrate includes the steps of sequentially depositing a polysilicon layer and a refractory metal silicide layer over a gate oxide and heating the same to form a polycide gate structure. After etching the polycide composite layer to define the gate, spacer oxide layers are formed to cover the lateral edges of the gate structure, and a transition metal layer is deposited over the bare polycide composite layer and the surrounding bare source and drain diffused silicon regions. The deposited transition metal layer is annealed to react with the polycide in the gate structure and thereby lower the sheet resistance of the gate. The transition metal also reacts with the source and drain regions to form silicides for lowering the sheet resistance of the source and drain regions. Unreacted transition metal is removed from the upper surface of the substrate, and subsequent glass deposition, contact opening, and metalization may be performed in the usual manner.

REFERENCES:
patent: 4180596 (1979-12-01), Crowder et al.
patent: 4622735 (1986-11-01), Shibata
C. Y. Ting, "Silicide for Contacts and Interconnects", IEDM, 1984, pp. 110-113.
Huang et al., "Eliminating Spacer-Induced Degradations in LDD Transistors", International Symposium on VLSI Technology Systems and Application, May 13, 1987, Taipei, Taiwan, R.O.C., p. 260-264.
S. M. Sze, VLSI Technology, Bell Lab., Incorporated, Murray Hill, N.J., 1983, published by McGraw-Hill Book Company, pp. 367-369.

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